Part I: Introduction, Parallel Computing Architectures, Serial Tuning - Monday, March 11

After an introduction to the principles of today's parallel computing architectures, the configuration of the new components of the RWTH Compute Cluster delivered by the company Bull will be explained. As good serial performance is the basis for good parallel performance, we cover serial tuning before introducing parallelization paradigms.

Please register here for Part I of PPCES 2013 

Part II: Message Passing with MPI - Tuesday, March 12

The Message Passing Interface (MPI) is the de-facto standard for programming large HPC Clusters. We will introduce the basic concepts and give an overview of some advanced features. Furthermore, we will introduce the TotalView debugger and a selection of performance tools. We will also cover hybrid parallelization, i.e. the combination of MPI and shared memory programming. Hybrid parallelization is gaining popularity as the number of cores per cluster node is growing.

Please register here for Part II of PPCES 2013

Part III: Shared Memory Programming with OpenMP - Wednesday, March 13 

Part IV: GPGPU Programming with OpenACC - Thursday, March 14

OpenACC is a directive-based programming model for accelerators which enables delegating the responsibility for low-level (e.g. CUDA or OpenCL) programming tasks to the compiler. To this end, using the OpenACC API, the programmer can offload compute-intensive loops to an attached accelerator with little effort. The open industry standard OpenACC has been introduced in November 2011 and supports accelerating regions of code in standard C, C++ and Fortran. It provides portability across operating systems, host CPUs and accelerators.

During this workshop day, we will give an overview on OpenACC while focusing on NVIDIA GPUs. We will introduce the GPU architecture and explain very briefly how a usual CUDA program looks like. Then, we will dive into OpenACC and learn about its possibilities to accelerate code regions. We will cover topics such as offloading loops, managing data movement between host and device, tuning data movement and accesses, applying loop schedules, using multiple GPUs or interoperate with CUDA libraries. At the end, we will give an outlook to the OpenMP 4.0 standard that may include OpenMP for accelerators. Hands-on sessions are done on the RWTH Aachen GPU (Fermi) Cluster using PGI's OpenACC implementation.

Part V: Programming the Intel® Xeon Phi™ Coprocessor, Tune your own Code - Friday, March 15

Accelerators, like GPUs, are one way to fulfill the requirement for more and more compute power. However, they often require a laborious rewrite of the application using special programming paradigms like CUDA or OpenCL.The Intel Xeon Phi coprocessor is based on the Intel Many Integrated Core Architecture and can be programmed with standard techniques like OpenMP, POSIX threads, or MPI. We will give a brief introduction to this new architecture and demonstrate the different programming possibilities. For the labs you can also continue working on lab exercises or to get started with porting or tuning your own codes (not only for Xeon Phi). Don‘t put your expectations too high though, as time for working on large codes is limited. You will profit more from this opportunity the better you are prepared.

Please register here for Part V of PPCES 2013 (Please mark if you attend the social dinner on Wed, March 13, 19:00)

Speakers

• Prof. Dr. Matthias Müller, RWTH Center for Computing and Communication
• Thomas Warschko, Bull GmbH
• Ruud van der Pas, Oracle
• Members of the HPC Team of the RWTH Center for Computing and Communication

Course Materials